IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2022
BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem.
Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only \(3\,777\) slices and performs a key generation, encapsulation, and decapsulation in \(3\,797 \mu s\), \(443 \mu s\), and \(6\,896 \mu s\), respectively. Our high-speed design requires \(7\,332\) slices and performs the three KEM operations in \(1\,672 \mu s\), \(132 \mu s\), and \(1\,892 \mu s\), respectively.